--- product_id: 81766718 title: "The RISC-V Reader: An Open Architecture Atlas" price: "COP 168646" currency: COP in_stock: true reviews_count: 13 url: https://www.desertcart.co/products/81766718-the-risc-v-reader-an-open-architecture-atlas store_origin: CO region: Colombia --- # The RISC-V Reader: An Open Architecture Atlas **Price:** COP 168646 **Availability:** ✅ In Stock ## Quick Answers - **What is this?** The RISC-V Reader: An Open Architecture Atlas - **How much does it cost?** COP 168646 with free shipping - **Is it available?** Yes, in stock and ready to ship - **Where can I buy it?** [www.desertcart.co](https://www.desertcart.co/products/81766718-the-risc-v-reader-an-open-architecture-atlas) ## Best For - Customers looking for quality international products ## Why This Product - Free international shipping included - Worldwide delivery with tracking - 15-day hassle-free returns ## Description The RISC-V Reader: An Open Architecture Atlas [Patterson, David, Waterman, Andrew] on desertcart.com. *FREE* shipping on qualifying offers. The RISC-V Reader: An Open Architecture Atlas Review: Great reference! - This offers an exceptional introduction to the RISC instruction set. I've seen other reduced instruction set computers - RISCs in the generic sense or gRISCs for now - but I find this distinctive in several ways. Regularity and orthogonality are nearly defining features of gRISCs, and RISC-V shares that. It goes farther, though. RISC-V, like gRISCs ARM and MIPS, has a compressed instruction format. But, unlike the others, RISC-V compressed instructions form a proper subset of the full-length instructions - regularity of yet another kind. Also like others, different RISC-V implementations might omit or include parts of the instruction set. Unlike the others, though, RISC-V clearly defines subsets, like floating point or vector operations, making it a bit easier for programmers to remember what's supported in any specific implementation. The modular instruction set also makes it easy for chip builders to trade off features and performance against complexity and cost in predictable ways. As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems. I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful. -- wiredweird Review: One of the developers is an author - Nice coverage of the RISC-V instruction set and what led to the development and why it is implemented like it is. Compares it with ARM and Intel processor instructions. Covers assembly language. ## Technical Specifications | Specification | Value | |---------------|-------| | Best Sellers Rank | #357,606 in Books ( See Top 100 in Books ) #512 in Computer Hardware & DIY | | Customer Reviews | 4.6 4.6 out of 5 stars (164) | | Dimensions | 7.5 x 0.46 x 9.25 inches | | ISBN-10 | 0999249118 | | ISBN-13 | 978-0999249116 | | Item Weight | 14.9 ounces | | Language | English | | Print length | 200 pages | | Publication date | November 7, 2017 | | Publisher | Strawberry Canyon | ## Images ![The RISC-V Reader: An Open Architecture Atlas - Image 1](https://m.media-amazon.com/images/I/51MWsWqjxFL.jpg) ![The RISC-V Reader: An Open Architecture Atlas - Image 2](https://m.media-amazon.com/images/I/51yY+bGSShL.jpg) ## Customer Reviews ### ⭐⭐⭐⭐⭐ Great reference! *by W***D on July 1, 2018* This offers an exceptional introduction to the RISC instruction set. I've seen other reduced instruction set computers - RISCs in the generic sense or gRISCs for now - but I find this distinctive in several ways. Regularity and orthogonality are nearly defining features of gRISCs, and RISC-V shares that. It goes farther, though. RISC-V, like gRISCs ARM and MIPS, has a compressed instruction format. But, unlike the others, RISC-V compressed instructions form a proper subset of the full-length instructions - regularity of yet another kind. Also like others, different RISC-V implementations might omit or include parts of the instruction set. Unlike the others, though, RISC-V clearly defines subsets, like floating point or vector operations, making it a bit easier for programmers to remember what's supported in any specific implementation. The modular instruction set also makes it easy for chip builders to trade off features and performance against complexity and cost in predictable ways. As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems. I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful. -- wiredweird ### ⭐⭐⭐⭐⭐ One of the developers is an author *by L***N on December 28, 2022* Nice coverage of the RISC-V instruction set and what led to the development and why it is implemented like it is. Compares it with ARM and Intel processor instructions. Covers assembly language. ### ⭐⭐⭐⭐ Very informative. A bit technical. *by A***B on March 3, 2022* This book is great for anyone looking to get into RISC-V development. I do suggest a background in programming as it can be a bit technical. ## Frequently Bought Together - The RISC-V Reader: An Open Architecture Atlas - RISC-V Assembly Language - Computer Organization and Design RISC-V Edition: The Hardware Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) --- ## Why Shop on Desertcart? - 🛒 **Trusted by 1.3+ Million Shoppers** — Serving international shoppers since 2016 - 🌍 **Shop Globally** — Access 737+ million products across 21 categories - 💰 **No Hidden Fees** — All customs, duties, and taxes included in the price - 🔄 **15-Day Free Returns** — Hassle-free returns (30 days for PRO members) - 🔒 **Secure Payments** — Trusted payment options with buyer protection - ⭐ **TrustPilot Rated 4.5/5** — Based on 8,000+ happy customer reviews **Shop now:** [https://www.desertcart.co/products/81766718-the-risc-v-reader-an-open-architecture-atlas](https://www.desertcart.co/products/81766718-the-risc-v-reader-an-open-architecture-atlas) --- *Product available on Desertcart Colombia* *Store origin: CO* *Last updated: 2026-04-22*